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Package Plan for Intel ® MAX ® 10 Dual Power Supply Devices Device Package Type V36 36-pin WLCSP V81 81-pin WLCSP U324 324-pin UBGA F256 256-pin FBGA F484 484-pin FBGA F672 672-pin FBGA Size 3 mm × 3 mm 4 mm × 4 mm 15 mm × 15 mm 17 mm × 17 mm 23 mm × 23 mm 27 mm × 27 mm Ball Pitch 0.4 mm 0.4 mm 0.8 mm 1.0 mm 1.0 mm 1.0 mm 10M02 27 — 160 — — — 10M04 — — 246 178 — — 10M08 — 56 246 178 250 — 10M16 — — 246 178 320 — 10M25 — — — 178 360 — 10M40 — — — 178 360 500 10M50 — — — 178 360 500 Intel MAX 10 I/O Vertical Migration Support. Supported I/O Standards in Intel ® MAX ® 10 Devices. The voltage-referenced I/O standards are not supported in the following I/O banks of these device packages: • All I/O banks of V36 package of 10M02. • All I/O banks of V81 package of 10M08. • Banks 1A and 1B of E144 package of 10M50.

I/O Standard Type Device Support Direction Application Standard Support Input Output 3.3 V LVTTL/3.3 V LVCMOS Single-ended All Yes Yes General purpose JESD8-B 3.0 V LVTTL/3.0 V LVCMOS Single-ended All Yes Yes General purpose JESD8-B 2.5 V LVCMOS Single-ended All Yes Yes General purpose JESD8-5 1.8 V LVCMOS Single-ended All Yes Yes General purpose JESD8-7 1.5 V LVCMOS Single-ended All Yes Yes General purpose JESD8-11 1.2 V LVCMOS Single-ended All Yes Yes General purpose JESD8-12 3.0 V PCI Single-ended All Yes Yes General purpose PCI Rev. Note: The I/O standards that each pin type supports depends on the I/O standards that the pin's I/O bank supports. For example, only the bottom I/O banks support the LVDS (dedicated) I/O standard. You can use the LVDS (dedicated) I/O standard for the PLL_CLKOUT pin only if the pin is available in your device's bottom I/O banks. To determine the pin's I/O bank locations for your device, check your device's pin out file.

The Intel ® MAX ® 10 I/O elements (IOEs) contain a bidirectional I/O buffer and five registers for registering input, output, output-enable signals, and complete embedded bidirectional single data rate (SDR) and double data rate (DDR) transfer. The I/O buffers are grouped into groups of four I/O modules per I/O bank: • The Intel ® MAX ® 10 devices share the user I/O pins with the VREF, RUP, RDN, CLKPIN, PLLCLKOUT, configuration, and test pins. • Schmitt Trigger input buffer is available in all I/O buffers. Each IOE contains one input register, two output registers, and two output-enable (OE) registers: • The two output registers and two OE registers are used for DDR applications. • You can use the input registers for fast setup times and output registers for fast clock-to-output times. • You can use the OE registers for fast clock-to-output enable times.

You can use the IOEs for input, output, or bidirectional data paths. The I/O pins support various single-ended and differential I/O standards. The I/O elements are located in a group of four modules per I/O bank: • High speed DDR3 I/O banks—supports various I/O standards and protocols including DDR3. These I/O banks are available only on the right side of the device. • High speed I/O banks—supports various I/O standards and protocols except DDR3.

These I/O banks are available on the top, left, and bottom sides of the device. • Low speed I/O banks—lower speeds I/O banks that are located at the top left side of the device.

For more information about I/O pins support, refer to the pinout files for your device. The performance of the I/O banks differs for different I/O standards and I/O bank types. You must ensure that the frequency you specified passes timing check in the Intel ® Quartus ® Prime software. The low speed I/O banks have lower maximum frequency than other I/O banks because of longer propagation delays. However, the delays do not affect the timing parameters such as slew rate, rise time, and fall time. For details about the location of the high speed and low speed I/O banks, refer to the device pinout files. Types of GPIO Buffers in Intel ® MAX ® 10 Devices LVDS I/O Buffers DDR I/O Buffers • Support differential and single-ended I/O standards.

• Available only on I/O banks at the bottom side of the device. • For LVDS, the bottom I/O banks support LVDS transmitter, emulated LVDS transmitter, and LVDS receiver buffers. • Support differential and single-ended I/O standards.

• Available on I/O banks at the left, right, and top sides of the device. • For LVDS, the DDR I/O buffers support only LVDS receiver and emulated LVDS transmitter buffers. • For DDR, only the DDR I/O buffers on the right side of the device supports DDR3 external memory interfaces. DDR3 support is only available for Intel ® MAX ® 10 16, 25, 40, and 50 devices. Summary of Supported Intel ® MAX ® 10 Programmable I/O Buffer Features and Settings Feature Setting Condition Assignment Name Supported I/O Standards Open Drain On, Off (default) To enable this feature, use the OPNDRN primitive. — • 3.0 V and 3.3 V LVTTL • 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, and 3.3 V LVCMOS • SSTL-2, SSTL-18, SSTL-15, and SSTL-135 • 1.2 V, 1.5 V, and 1.8 V HSTL • HSUL-12 • 3.0 V PCI Bus-Hold On, Off (default) Disabled if you use the weak pull-up resistor feature. Enable Bus-Hold Circuitry Pull-up Resistor On, Off (default) Disabled if you use the bus-hold feature.

Weak Pull-Up Resistor Slew Rate Control 0 (Slow), 1 (Medium), 2 (Fast). Default is 2.

Disabled if you use OCT. Slew Rate • 3.0 V LVTTL • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.0 V LVCMOS • SSTL-2, SSTL-18, and SSTL-15 • 1.2 V, 1.5 V, and 1.8 V HSTL • Differential SSTL-2, Differential SSTL-18, and Differential SSTL-15 • Differential 1.2 V, 1.5 V, and 1.8 V HSTL PCI Clamp Diode On (default for input pins), Off (default for output pins, except 3.0 V PCI) — PCI I/O • 3.0 V and 3.3 V LVTTL • 2.5 V, 3.0 V, and 3.3 V LVCMOS • 3.0 V PCI • 2.5 V, 3.0 V, and 3.3 V Schmitt Trigger Pre-Emphasis 0 (disabled), 1 (enabled). Default is 1.

— Programmable Pre-emphasis • LVDS • RSDS • PPDS • Mini-LVDS Differential Output Voltage 0 (low), 1 (medium), 2 (high). Default is 2. — Programmable Differential Output Voltage (V OD). User I/O pins can be in either the default weak pull-up state or tri-state during configuration. With the bus-hold feature, if you do not drive the I/O pin externally when it enters user mode from configuration mode: • The I/O pin state is weak pull-up during configuration—the I/O pin retains the high value when the device enters user mode.

• The I/O pin is tri-stated during configuration—the I/O pin value can be high or low when the device enters user mode. For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the V CCIO level.

If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the I/O pin for differential signals, disable the bus-hold feature. Programmable Pull-Up Resistor. Programmable Current Strength Settings for Intel ® MAX ® 10 Devices.

The output buffer for each Intel ® MAX ® 10 device I/O pin has a programmable current strength control for the I/O standards listed in this table. Programmable Output Slew Rate Control for Intel ® MAX ® 10 Devices. This table lists the single-ended I/O standards and current strength settings that support programmable output slew rate control. For I/O standards and current strength settings that do not support programmable slew rate control, the default slew rate setting is 2 (fast slew rate). Programmable Delay Chain Programmable Delays Intel ® Quartus ® Prime Logic Option Input pin-to-logic array delay Input delay from pin to internal cells Input pin-to-input register delay Input delay from pin to input register Output pin delay Delay from output register to output pin Dual-purpose clock input pin delay Input delay from dual-purpose clock pin to fan-out destinations There are two paths in the IOE for an input to reach the logic array.

Each of the two paths can have a different delay. This allows you to adjust delays from the pin to the internal logic element (LE) registers that reside in two different areas of the device. You must set the two combinational input delays with the input delay from pin to internal cells logic option in the Intel ® Quartus ® Prime software for each path. If the pin uses the input register, one of the delays is disregarded and the delay is set with the input delay from pin to input register logic option in the Intel ® Quartus ® Prime software. The IOE registers in each I/O block share the same source for the preset or clear features.

You can program preset or clear for each individual IOE, but you cannot use both features simultaneously. You can also program the registers to power-up high or low after configuration is complete.

If programmed to power-up low, an asynchronous clear can control the registers. If programmed to power-up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of the active-low input of another device upon power up.

If one register in an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available for the IOE registers. The Intel ® MAX ® 10 devices are equipped with optional PCI clamp diode that you can enable for the input and output of each I/O pin. The PCI clamp diode is available in the Intel ® Quartus ® Prime software for the following I/O standards: • 3.3 V LVTTL/3.3 V LVCMOS • 3.0 V LVTTL/3.0 V LVCMOS • 2.5 V LVTTL/2.5 V LVCMOS • 3.0 V PCI • 3.3 V Schmitt Trigger • 2.5 V Schmitt Trigger Dual-purpose configuration pins support the diode in user mode if you do not use the pins as configuration pins for the selected configuration scheme.

The dedicated configuration pins do not support the on-chip diode. Programmable Pre-Emphasis. The differential output voltage (V OD) setting and the output impedance of the driver set the output current limit of a high-speed transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full V OD level before the next edge, producing pattern-dependent jitter. Pre-emphasis momentarily boosts the output current during switching to increase the output slew rate.

Pre-emphasis increases the amplitude of the high-frequency component of the output signal. This increase compensates for the frequency-dependent attenuation along the transmission line. The overshoot introduced by the extra current occurs only during change of state switching.

This overshoot increases the output slew rate but does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line. The Intel ® MAX ® 10 devices support emulated differential output where a pair of IOEs drives bidirectional I/O pins.

The emulated differential output feature is supported for the following I/O standards: • Differential SSTL-2 Class I and II • Differential SSTL-18 Class I and II • Differential SSTL-15 Class I and II • Differential SSTL-15 • Differential SSTL-135 • Differential 1.8 V HSTL Class I and II • Differential 1.5 V HSTL Class I and II • Differential 1.2 V HSTL Class I and II • Differential HSUL-12 • LVDS 3R • Mini-LVDS 3R • PPDS 3R • RSDS 1R and 3R • BLVDS • SLVS • Sub-LVDS Programmable Dynamic Power Down. The OCT calibration circuit compares the total impedance of the output buffer to the external resistors connected to the RUP and RDN pins.

The circuit dynamically adjusts the output buffer impedance until it matches the external resisters. Each calibration block comes with a pair of RUP and RDN pins.

During calibration, the RUP and RDN pins are each connected through an external 25 Ω, 34 Ω, 40 Ω, 48 Ω, or 50 Ω resistor for respective on-chip series termination value of 25 Ω, 34 Ω, 40 Ω, 48 Ω, and 50 Ω: • RUP—connected to VCCIO. • RDN—connected to GND. The OCT calibration circuit compares the external resistors to the internal resistance using comparators. The OCT calibration block uses the comparators' output to dynamically adjust buffer impedance. During calibration, the resistance of the RUP and RDN pins varies.

To estimate of the maximum possible current through the external calibration resistors, assume a minimum resistance of 0 Ω on the RUP and RDN pins. RS OCT in Intel MAX 10 Devices. Selectable I/O Standards for R S OCT. This table lists the output termination settings for R S OCT with and without calibration on different I/O standards. • R S OCT with calibration—supported only on the right side I/O banks of the Intel ® MAX ® 10 16, 25, 40, and 50 devices.

• R S OCT without calibration—supported on all I/O banks of all Intel ® MAX ® 10 devices. There are several V CCIO range considerations because of I/O pin configuration function and I/O bank location. • The shared I/O pins can only support a V CCIO range of 1.5 V to 3.3 V when you access the configuration function in user mode. The configuration function of the I/O pins can only support 1.5 V to 3.3 V. If you need to access, for example, JTAG pins during user mode, the bank where the pin resides will be constrained by this V CCIO range.

If you want to use I/O standards within the 1.2 V to 1.35 V range, you must not use the configuration function of any of the I/O pins during user mode. This only affects bank 1 and bank 8 because only these banks have I/O pins with configuration function. • For devices with banks 1A and 1B: • If you use the VREF pin or the ADC, you must supply a common V CCIO voltage to banks 1A and 1B. • If you do not use the VREF pin or the ADC, you can supply separate V CCIO voltages to banks 1A and 1B. • If you plan to migrate from devices that has banks 1A and 1B to devices that has only bank 1, ensure that the V CCIO of bank 1A and 1B are the same.

• For the V36 package of the 10M02 device, the V CCIO of these groups of I/O banks must be the same: • Group 1—banks 1, 2 and 8 • Group 2—banks 3, 5, and 6 • For the V81 package of the 10M08 device, the V CCIO of these groups of I/O banks must be the same: • Group 1—banks 1A, 1B, and 2 • Group 2—banks 5 and 6 Guidelines: Voltage-Referenced I/O Standards Restriction. These restrictions apply if you use the V REF pin. • If you use a shared VREF pin as an I/O, all voltage-reference input buffers (SSTL, HSTL, and HSUL) are disabled. • If you use a shared VREF pin as a voltage reference, you must enable the input buffer of specific I/O pin to use the voltage-reference I/O standards. • The voltage-referenced I/O standards are not supported in the following I/O banks of these device packages: • All I/O banks of V36 package of 10M02. • All I/O banks of V81 package of 10M08.

• Banks 1A and 1B of E144 package of 10M50. • For devices with banks 1A and 1B, if you use the VREF pin, you must supply a common V CCIO to banks 1A and 1B. • Maximum number of voltage-referenced inputs for each VREF pin is 75% of total number of I/O pads. The Intel ® Quartus ® Prime software will provide a warning if you exceed the maximum number. • Except for I/O pins that you used for static signals, all non-voltage-referenced output must be placed two pads away from a VREF pin. The Intel ® Quartus ® Prime software will output an error message if this rule is violated.

If the input voltage to the LVTTL/LVCMOS input buffers is higher than the V CCIO of the I/O bank, Intel recommends that you enable the clamp diode. • 3.3 V LVCMOS/LVTTL input buffers—enable clamp diode if V CCIO of the I/O bank is 3.0 V.

• 3.3 V or 3.0 V LVCMOS/LVTTL input buffers—enable clamp diode if V CCIO of the I/O bank is 2.5 V. By enabling the clamp diode under these conditions, you limit overshoot or undershoot. However, this does not comply with hot socket current specification. If you do not enable the clamp diode under these conditions, the signal integrity for the I/O pin is impacted and there will be overshoot or undershoot problem. In this situation, you must ensure that your board design coreduce firefox cachenforms to the overshoot/undershoot specifications. Maximum Percentage of I/O Pins Allowed for Specific I/O Standards in an I/O Bank.

This table lists the maximum number of general purpose output pins recommended in a bank in terms of percentage to the total number of I/O pins available in an I/O bank if you use these combinations of I/O standards and conditions. I/O Standard Condition Max Pins Per Bank (%) 2.5 V LVTTL/LVCMOS 16 mA current strength and 25 Ω OCT (fast and slow slew rate) 25 12 mA current strength (fast and slow slew rate) 30 8 mA current strength (fast and slow slew rate) and 50 Ω OCT (fast slew rate) 45 4 mA current strength (fast and slow slew rate) 65 2.5 V SSTL — 100 Guidelines: Analog-to-Digital Converter I/O Restriction. These restrictions are applicable if you use the analog-to-digital converter (ADC) block. The Intel ® Quartus ® Prime software uses physics-based rules to define the number of I/Os allowed in a particular bank based on the I/O's drive strength. These rules are based on noise calculation to analyze accurately the impact of I/O placement on the ADC performance. The physics-based rules are available for the following devices starting from these Intel ® Quartus ® Prime software versions: • From Intel ® Quartus ® Prime version 14.1— Intel ® MAX ® 10 10M04, 10M08, 10M40, and 10M50 devices.

• From Intel ® Quartus ® Prime version 15.0.1— Intel ® MAX ® 10 10M02, 10M16, and 10M25 devices. Geometry-Based I/O Restrictions Related to ADC Usage. This table lists the I/O restrictions by Intel ® MAX ® 10 device package if you use the dedicated analog input ( ANAIN1 or ANAIN2) or any dual function ADC I/O pins as ADC channel inputs. Package Restriction/Guideline All Disable all JTAG operation during ADC sampling. The ADC signal-to-noise and distortion ratio (SINAD) is not guaranteed during JTAG operation. M153 U169 U324 F256 F484 F672 • Banks 1A and 1B—you cannot use GPIO pins in these banks. • Banks 2, 3, 4, 5, 6, and 7—you can use GPIO pins located in these banks.

• Bank 8—you can use a percentage of the GPIO pins in this bank based on drive strength: • For an example listing the percentage of GPIO pins allowed in bank 8 for the F484 package, refer to. • Use low drive strength ( 8 mA and below) and differential I/O standards. • Do not place transmitter pins in this bank. Use banks 2, 3, 4, 5, 6, or 7 instead.

• You can use static pins such as RESET or CONTROL. • GPIO pins in this bank are governed by physics-based rules. The Intel ® Quartus ® Prime software will issue a critical warning I/O settings violates any of the I/O physic-based rule. E144 • Bank 1A, 1B, 2, and 8—you cannot use GPIO pins in these banks. • Banks 4 and 6—you can use GPIO pins located in these banks.

• Banks 3, 5, and 7—you can use a percentage of the GPIO pins in this bank based on drive strength: • For the percentage of GPIO pins allowed, refer to. • Use low drive strength ( 8 mA and below) and differential I/O standards. • GPIO pins in these banks are governed by physics-based rules. The Intel ® Quartus ® Prime software will issue a critical warning I/O settings violates any of the I/O physic-based rule. I/O Usage Restriction for Banks 3, 5, and 7 in Intel ® MAX ® 10 E144 Package.

This table lists the percentage of I/O pins available in banks 3, 5, and 7 if you use the dedicated analog input ( ANAIN1 or ANAIN2) or any dual function ADC I/O pins as ADC channel inputs. Refer to for the list of I/O standards in each group. I/O Standards Bank 3 Bank 5 Bank 7 Device I/O Availability (%) TX RX Availability (%) TX RX Availability (%) TX RX Availability (%) Group 1 7 8 88 6 6 100 4 3 100 54 Group 2 7 8 88 6 6 100 4 3 100 54 Group 3 4 5 50 6 6 100 2 0 29 45 Group 4 3 4 39 5 5 83 0 0 0 39 Group 5 2 3 28 5 5 83 0 0 0 37 Group 6 1 2 17 5 5 83 0 0 0 35 Group 7 0 0 0 5 5 83 0 0 0 32.

Total I/O Utilization in Bank Must Be 75 Percent or Less in Some Devices If you use DDR3 or LPDDR2 SDRAM memory interface standards, you can generally use a maximum of 75 percent of the total number of I/O pins available in a bank. This restriction differs from device to device.

In some devices packages you can use all 100 percent of the I/Os. The Intel ® Quartus ® Prime software will output an error message if the I/O usage per bank of that device is affected by this rule. If you use DDR2 memory interface standards, you can assign 25 percent of the I/O pins as input pins only. Guidelines: Dual-Purpose Configuration Pin.

Dual-Purpose Configuration Pin Guidelines for Intel ® MAX ® 10 Devices Guidelines Pins Configuration pins during initialization: • Tri-state the external I/O driver and drive an external pull-up resistor or • Use the external I/O driver to drive the pins to the state same as the external weak pull-up resistor • nCONFIG • nSTATUS • CONF_DONE JTAG pins: • If you intend to switch back and forth between user I/O pins and JTAG pin functions using the JTAGEN pin, all JTAG pins must be assigned as single-ended I/O pins or voltage-referenced I/O pins. Schmitt trigger input is the recommended input buffer. • JTAG pins cannot perform as JTAG pins in user mode if you assign any of the JTAG pin as a differential I/O pin. • You must use the JTAG pins as dedicated pins and not as user I/O pins during JTAG programming. • Do not toggle JTAG pin during the initialization stage. • Put the test access port (TAP) controller in reset state by driving the TDI and TMS pins high and TCK pin low for at least 5 clock cycles before the initialization.

• TDO • TMS • TCK • TDI. Potential glitch on the data input pin, leading to input read signal failure, can occur in the following conditions: • The output pin directly adjacent to the data input pin is assigned an unterminated I/O standard, such as LVTTL and LVCMOS, with drive strength of 8 mA or higher. • The output pin directly adjacent to the data input pin is assigned a terminated I/O standard, such as SSTL, with drive strength of 8 mA or higher. Intel recommends that you implement these guidelines to reduce jitter on the data input pin: • For unterminated I/O standards, implement one of these guidelines: • For the directly-adjacent output pin with these unterminated I/O standards, reduce the drive strength as follows: • 2.5 V, 3.0 V, and 3.3 V—reduce to 4 mA or below • 1.2 V, 1.5 V, and 1.8 V—reduce to 6 mA or below • Assign the pins directly on the left and right of the data input pin to a non-toggling signal. • Change the data input pin to a Schmitt Trigger input buffer for better noise immunity.

If you are using Schmitt Trigger input buffer on the data input pin, you can use the directly-adjacent output pin with unterminated I/O standard at a maximum drive strength of 8 mA. • For terminated I/O standard, you can use only one pin directly on the left or right of the data input pin as toggling signal, provided that you set the slew rate setting of this pin to “ 0” (slow slew rate). Otherwise, assign the pins directly on the left and right of the data input pin to a non-toggling signal. Intel MAX 10 I/O Implementation Guides. The Altera GPIO Lite IP core supports the Intel ® MAX ® 10 GPIO components.

To implement the GPIOs in your design, you can customize the Altera GPIO Lite IP core to suit your requirements and instantiate it in your design. GPIOs are I/Os used in general applications not specific to transceivers, memory-like interfaces or LVDS. The Altera GPIO Lite IP core features the following components: • Double data rate input/output (DDIO)—A digital component that doubles the data-rate of a communication channel. • I/O buffers—connect the pads to the FPGA.

Altera GPIO Lite Data Path Modes Data Path Mode Bypass Single Register DDR Input Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). The full-rate DDIO operates as a single register. The full-rate DDIO operates as a regular DDIO. Output Data goes from the core straight to the delay element, bypassing all DDIOs. The full-rate DDIO operates as a single register.

The full-rate DDIO operates as a regular DDIO. Bidirectional The output buffer drives both an output pin and an input buffer. The full-rate DDIO operates as a single register.

The output buffer drives both an output pin and an input buffer. The full-rate DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer.

The input buffer drives a set of three flip-flops. If you use asynchronous clear and preset signals, all DDIOs share these same signals. • The IP core feeds the first bit, D0, through IO_DATAOUT1 to RegDo. The IP core clocks out this bit at the RegDo QB port on a negative clock edge. At the next positive clock edge, the IP core produces the same bit at the multiplexer output.

• The IP core feeds the second bit, D1, through IO_DATAOUT0 to RegCo. The IP core clocks out this bit at the RegCo Q port on a positive clock edge. At the next negative clock edge, the IP core produces the same bit at the multiplexer output. Verifying Pin Migration Compatibility. You can vertically migrate to a device with a different density while using the same device package, or migrate between packages with different densities and ball counts. • Open Assignments >Pin Planner and create pin assignments. • If necessary, perform one of the following options to populate the Pin Planner with the node names in the design: • Analysis & Elaboration • Analysis & Synthesis • Fully compile the design • Then, on the menu, click View >Pin Migration Window.

• To select or change migration devices: • Click Device to open the Device dialog box. • Click Migration Devices. • To show more information about the pins: • Right-click anywhere in the Pin Migration View window and select Show Columns. • Then, click the pin feature you want to display.

• If you want to view only the pins, in at least one migration device, that have a different feature than the corresponding pin in the migration result, turn on Show migration differences. • Click Pin Finder to open the Pin Finder dialog box and find and highlight pins with specific functionality.

Altera GPIO Lite Parameters - Buffer Parameter Condition Allowed Values Description Use true differential buffer Data direction = input or output • On • Off If turned on, enables true differential I/O buffers and disables pseudo differential I/O buffers. Use pseudo differential buffer Data direction = output or bidir • On • Off • If turned on in output mode—enables pseudo differential output buffers and disables true differential I/O buffers. • If turned on in bidir mode—enables true differential input buffer and pseudo differential output buffer. Use bus-hold circuitry Data direction = input or output • On • Off If turned on, the bus hold circuitry can weakly hold the signal on an I/O pin at its last-driven state where the output buffer state will be 1 or 0 but not high-impedance. Use open drain output Data direction = output or bidir • On • Off If turned on, the open drain output enables the device to provide system-level control signals such as interrupt and write enable signals that can be asserted by multiple devices in your system.

Enable oe port Data direction = output • On • Off If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode. Enable nsleep port (only available in selected devices) Data direction = input or bidir • On • Off If turned on, enables the nsleep port. This option is available for the 10M16, 10M25, 10M40, and 10M50 devices. Altera GPIO Lite Parameters - Registers Parameter Condition Allowed Values Description Register mode — • bypass • single-register • ddr Specifies the register mode for the Altera GPIO Lite IP core: • bypass—specifies a simple wire connection from/to the buffer. • single-register—specifies that the DDIO is used as a simple register in single data-rate mode (SDR).

The Fitter may pack this register in the I/O. • ddr— specifies that the IP core uses the DDIO. Enable aclr port • Register mode = ddr • On • Off If turned on, enables the ACLR port for asynchronous clears. Enable aset port • Data direction = output or bidir • Register mode = ddr • Set registers to power up high (when aclr and aset ports are not used) = off • On • Off If turned on, enables the ASET port for asynchronous preset. Set registers to power up high (when aclr and aset ports are not used) • Register mode = ddr • Enable aclr port = off • Enable aset port = off • Enable sclr port = off • On • Off If you are not using the ACLR and ASET ports: • On—specifies that registers power up HIGH. • Off—specifies that registers power up LOW. Enable inclocken/outclocken ports Register mode = ddr • On • Off • On—exposes the clock enable port to allow you to control when data is clocked in or out.

This signal prevents data from being passed through without your control. • Off—clock enable port is not exposed and data always pass through the register automatically. Invert din • Data direction = output • Register mode = ddr • On • Off If turned on, inverts the data out output port. Invert DDIO inclock • Data direction = input or bidir • Register mode = ddr • On • Off • On—captures the first data bit on the falling edge of the input clock. • Off—captures the first data bit on the rising edge of the input clock.

Use a single register to drive the output enable (oe) signal at the I/O buffer • Data direction = output or bidir • Register mode = single-register or ddr • Use DDIO registers to drive the output enable (oe) signal at the I/O buffer = off • On • Off If turned on, specifies that a single register drives the OE signal at the output buffer. Use DDIO registers to drive the output enable (oe) signal at the I/O buffer • Data direction = output or bidir • Register mode = ddr • Use a single register to drive the output enable (oe) signal at the I/O buffer = off • On • Off If turned on, specifies that the DDR I/O registers drive the OE signal at the output buffer. The output pin is held at high impedance for an extra half clock cycle after the OE port goes high.

Implement DDIO input registers in hard implementation (Only available in certain devices) • Data direction = input or bidir • Register mode = ddr • On • Off • On—implements the DDIO input registers using hard block at the I/O edge. • Off—implements the DDIO input registers as soft implementation using registers in the FPGA core fabric. This option is applicable only for Intel ® MAX ® 10 16, 25, 40, and 50 devices because the DDIO input registers hard block is available only in these devices.

To avoid Fitter error, turn this option off for other Intel ® MAX ® 10 devices. Altera GPIO Lite Interface Signals. Pad Interface Signals. The pad interface connects the Altera GPIO Lite IP core to the pads.

Signal Name Direction Description pad_in Input Input pad port if you use the input path. Pad_in_b Input Input negative pad port if you use the input path and enable the true or pseudo differential buffers. Pad_out Output Output pad port if you use the output path. Pad_out_b Output Output negative pad port if you use the output path and enable the true of pseudo differential buffers. Pad_io Bidirectional Bidirectional pad port if you use bidirectional paths. Pad_io_b Bidirectional Bidirectional negative pad port if you use bidirectional paths and enable true or pseudo differential buffers.

Data Interface Signals. The data interface is an input or output interface from the Altera GPIO Lite IP core to the FPGA core. Signal Name Direction Description din Input Data received from the input pin. Signal width for each input pin: • DDR mode—2 • Other modes—1 dout Output Data to send out through the output pin. Signal width for each output pin: • DDR mode—2 • Other modes—1 oe Input Control signal that enables the output buffer. This signal is active HIGH. Nsleep Input Control signal that enables the input buffer.

This signal is active LOW. This signal is available for the 10M16, 10M25, 10M40, and 10M50 devices. Clock Interface Signals. The clock interface is an input clock interface.

It consists of different signals, depending on the configuration. The Altera GPIO Lite IP core can have zero, one, two, or four clock inputs. Clock ports appear differently in different configurations to reflect the actual function performed by the clock signal.

Signal Name Direction Description inclock Input Input clock that clocks the registers in the input path. Inclocken Input Control signal that controls when data is clocked in. This signal is active HIGH. Outclock Input Input clock that clocks the registers in the output path. Ouctlocken Input Control signal that controls when data is clocked out.

This signal is active HIGH. Reset Interface Signals. The reset interface connects the Altera GPIO Lite IP core to the DDIOs.

Signal Name Direction Description aclr Input Control signal for asynchronous clear that sets the register output state to 0. This signal is active HIGH. Aset Input Control signal for asynchronous preset that sets the register output state to 1. This signal is active HIGH.

Sclr Input Control signal for synchronous clear that sets the register output to 0. This signal is active HIGH.

Intel MAX 10 General Purpose I/O User Guide Archives. Date Version Changes December 2017 2017.12.15 • Added the U324 package for the Intel ® MAX ® 10 single power supply devices. • Updated the I/O vertical migration figure. • Added a topic about the different I/O banks performance. • Updated the Altera GPIO Lite DDR output path figure, timing diagram, and added descriptions to improve clarity. • Updated the description in the guideline topic about I/O restrictions to improve clarity.

• Updated the guideline topic about the clock and data input signal for the E144 package to improve clarity. Hach Bod Incubator Model 205 Manual High School more. • Updated the guideline topic about the ADC I/O restriction to clarify that the guidelines are geometry-based rules for design estimation purpose. • Removed all 'Preliminary' markers. • Updated the topic about the PCI clamp diode to remove the sentence that mention the active serial (AS) configuration scheme.

Intel ® MAX ® 10 devices do not support the AS configuration scheme. • Updated the guideline topic about enabling the clamp diode for the LVTTL/LVCMOS input buffers to improve clarity. February 2017 2017.02.21 Rebranded as Intel. May 2016 2016.05.02 • Updated the list of supported I/O standards to specify I/O standards that are supported only in dual power supply Intel ® MAX ® 10 devices.

• Updated the names of emulated differential I/O standards to improve clarity. • Updated the topic about the I/O standards voltage and pin support to clarify that the I/O standards that a pin type supports depends on pin's I/O bank.

• Updated the setting information for PCI clamp diode: • On by default for input pins for all supported I/O standards • Off by default for output pins for all supported I/O standards, except 3.0 V PCI • Updated the topic about the ADC I/O restriction: • Added the list of devices with physics-based rules support from Intel ® Quartus ® Prime version 15.0.1. • Clarified that the table listing the percentage of GPIOs allowed in bank 8 is an example for the F484 package.

For all packages, the Intel ® Quartus ® Prime software displays a warning message if you exceed the allowed GPIO percentage. November 2015 2015.11.02 • Added PCI clamp diode support for the 3.3 V and 2.5 V Schmitt Trigger I/O standards. • Added a table that summarizes the programmable I/O buffer features and settings. • Updated the topics about V CCIO range consideration and VREF I/O standards restriction with guidelines for using different V CCIO supplies in bank 1A and bank 1B.

• Added guidelines topic about using the clock and input pins in the E144 package. • Added the Enable nsleep port parameter option. • Removed the topics about the IP catalog and parameter editor, generating IP cores, and the files generated by the IP core, and added a link to Introduction to Intel IP Cores. • Changed instances of Quartus II to Quartus Prime. June 2015 2015.06.10 • Added related link to the Intel ® MAX ® 10 device pin-outs in topic about I/O banks locations. The device pin-out files provide more information about available I/O pins in each I/O bank. • Updated the ADC I/O restriction guidelines topic.

May 2015 2015.05.04 • Removed the F672 package of the Intel ® MAX ® 10 10M25 device. • Updated footnote for LVDS (dedicated) in the table listing the supported I/O standards to clarify that you can use LVDS receivers on all I/O banks. • Added missing footnote number for the DQS column of the 3.3 V Schmitt Trigger row in the table that lists the I/O standards voltage levels and pin support.

• Added a table listing the I/O standards and current strength settings that support programmable output slew rate control. • Updated the topic about external memory interface I/O restrictions to add x24 memory interface width to the F484 package.

• Added topic about the programmable differential output voltage. • Updated the guidelines for voltage-referenced I/O standards to add a list of device packages that do not support voltage-referenced I/O standards. • Updated the topic about the I/O restriction rules to remove statements about the differential pad placement rules. • Renamed the input_ena signal name to nsleep and updated the relevant description. • Updated the description for the Invert DDIO inclock parameter of the Altera GPIO Lite IP core.

December 2014 2014.12.15 Updated the topic about the ADC I/O restriction: • Added information about implementation of physics-based rules in the Intel ® Quartus ® Prime software. • Updated the list of I/O standards groups for the ADC I/O restriction. September 2014 2014.09.22 Initial release.